Invention Grant
US07900177B2 Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device
有权
基于布线图案的边界长度和密度，半导体设计装置和半导体器件处理虚设图案的方法
- Patent Title: Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device
- Patent Title (中): 基于布线图案的边界长度和密度，半导体设计装置和半导体器件处理虚设图案的方法
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Application No.: US12007439Application Date: 2008-01-10
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Publication No.: US07900177B2Publication Date: 2011-03-01
- Inventor: Keisuke Hirabayashi
- Applicant: Keisuke Hirabayashi
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2007-003173 20070111
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method of placing a dummy pattern in a wiring region includes calculating a density of a wiring pattern in the wiring region and calculating a value of a length of a periphery of the wiring pattern. The dummy pattern is then set such that a total of the pattern density and the value of the length of the periphery of the wiring pattern and the dummy pattern in the wiring region falls within specified ranges in the wiring region.
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