Invention Grant
- Patent Title: Method for manufacturing package on package with cavity
- Patent Title (中): 封装封装封装方法
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Application No.: US12585235Application Date: 2009-09-09
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Publication No.: US07901985B2Publication Date: 2011-03-08
- Inventor: Jee-Soo Mok , Chang-Sup Ryu , Dong-Jin Park
- Applicant: Jee-Soo Mok , Chang-Sup Ryu , Dong-Jin Park
- Applicant Address: KR Suwon
- Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee Address: KR Suwon
- Priority: KR10-2006-0014917 20060216
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A manufacturing method of a package on package with a cavity. The method can include forming a first upper substrate cavity in one side of an upper substrate; mounting an upper semiconductor chip on the other side of the upper substrate; forming a lower substrate cavity in one side of a lower substrate; mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate; and stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. The package on package and a manufacturing method thereof can reduce the overall thickness of the package by forming cavities in both upper and lower substrates to accommodate a semiconductor chip mounted in the lower substrate.
Public/Granted literature
- US20100022052A1 Method for manufacturing package on package with cavity Public/Granted day:2010-01-28
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