Invention Grant
US07902004B2 ESD induced artifact reduction design for a thin film transistor image sensor array
有权
用于薄膜晶体管图像传感器阵列的ESD诱导伪影设计
- Patent Title: ESD induced artifact reduction design for a thin film transistor image sensor array
- Patent Title (中): 用于薄膜晶体管图像传感器阵列的ESD诱导伪影设计
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Application No.: US12250780Application Date: 2008-10-14
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Publication No.: US07902004B2Publication Date: 2011-03-08
- Inventor: Richard Weisfield , Kungang Zhou , David Doan
- Applicant: Richard Weisfield , Kungang Zhou , David Doan
- Applicant Address: US CA Palo Alto
- Assignee: dpiX LLC
- Current Assignee: dpiX LLC
- Current Assignee Address: US CA Palo Alto
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/84

Abstract:
A method is provided for fabricating an image sensor array in a manner that reduces the potential for defects resulting from electrostatic discharge events during fabrication of the image sensor array. The method includes: forming at least one pixel over a substrate, the pixel including a switching transistor and a photo-sensitive cell; and forming a dielectric interlayer over the pixel. A key step in the method of the present invention is depositing a first conductive layer over the dielectric interlayer. After the first conductive layer is formed, the image sensor array is well protected from ESD events because the first conductive layer spreads out any charge induced by tribo-electric charging events that may occur during subsequent fabrication processing steps, thereby reducing the potential for localized damage to the switching transistors upon the occurrence of ESD events.
Public/Granted literature
- US20100091149A1 ESD INDUCED ARTIFACT REDUCTION DESIGN FOR A THIN FILM TRANSISTOR IMAGE SENSOR ARRAY Public/Granted day:2010-04-15
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