Invention Grant
- Patent Title: Methods for fabricating a stressed MOS device
- Patent Title (中): 制造应力MOS器件的方法
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Application No.: US11197046Application Date: 2005-08-03
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Publication No.: US07902008B2Publication Date: 2011-03-08
- Inventor: Igor Peidous , Mario M. Pelella
- Applicant: Igor Peidous , Mario M. Pelella
- Applicant Address: KY Grand Cayman
- Assignee: GlobalFoundries Inc.
- Current Assignee: GlobalFoundries Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/336

Abstract:
A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode. A stress inducing material is selectively grown in the first trench and in the second trench and conductivity determining impurity ions are implanted into the stress inducing material to form a source region in the first trench and a drain region in the second trench. To preserve the stress induced in the substrate, a layer of mechanically hard material is deposited on the stress inducing material after the step of ion implanting.
Public/Granted literature
- US20070032024A1 Methods for fabricating a stressed MOS device Public/Granted day:2007-02-08
Information query
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