Invention Grant
US07902021B2 Method for separately optimizing spacer width for two or more transistor classes using a recess spacer integration
有权
使用凹槽间隔物集成分别优化两个或多个晶体管类别的间隔物宽度的方法
- Patent Title: Method for separately optimizing spacer width for two or more transistor classes using a recess spacer integration
- Patent Title (中): 使用凹槽间隔物集成分别优化两个或多个晶体管类别的间隔物宽度的方法
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Application No.: US11365059Application Date: 2006-02-28
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Publication No.: US07902021B2Publication Date: 2011-03-08
- Inventor: Anadi Srivastava
- Applicant: Anadi Srivastava
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Fortkort & Houston P.C.
- Agent John A. Fortkort
- Main IPC: H01L21/8238
- IPC: H01L21/8238
Abstract:
A method for making a semiconductor device is disclosed. In accordance with the method, a semiconductor structure is provided which includes (a) a substrate (203), (b) first and second gate electrodes (219) disposed over the substrate, each of the first and second gate electrodes having first and second sidewalls, and (c) first (223) and second (225) sets of spacer structures disposed adjacent to the first and second gate electrodes, respectively. A first layer of photoresist (231) is then disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered, after which the first set of spacer structures is partially etched.
Public/Granted literature
Information query
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