An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ≦1010 dislocation lines/cm2 and an active concentration of the compressive strain inducing specie that is above a solid solubility limit for the compressive strain inducing specie in the compressive strain inducing region. A method for forming compressively strained PMOS transistors includes implanting on at least opposing sides of the gate stack using at least one compressive strain inducing specie selected from Ge, Sn and Pb at a dose ≧1×1015 cm−2, at an implantation temperature during implanting in a temperature range ≦273 K, wherein the implant conditions are sufficient to form an amorphous region. The wafer is annealed using annealing conditions including a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at the peak temperature of ≦10 seconds, wherein the amorphous region recrystallizes by solid phase epitaxy (SPE).