Methods of forming void-free layers in openings of semiconductor substrates

Invention Grant

US07902059B2 Methods of forming void-free layers in openings of semiconductor substrates 失效

Title translation: 在半导体衬底的开口中形成无空隙层的方法

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Patent Title: Methods of forming void-free layers in openings of semiconductor substrates
Patent Title (中): 在半导体衬底的开口中形成无空隙层的方法
Application No.: US12608579

Application Date: 2009-10-29
Publication No.: US07902059B2

Publication Date: 2011-03-08
Inventor: Jung-Hwan Kim , Hun-Hyeoung Leam , Jai-Dong Lee , Young-Seok Kim , Young-Sub You , Ki-Su Na , Woong Lee
Applicant: Jung-Hwan Kim , Hun-Hyeoung Leam , Jai-Dong Lee , Young-Seok Kim , Young-Sub You , Ki-Su Na , Woong Lee
Applicant Address: KR
Assignee: Samsung Electronics Co., Ltd.
Current Assignee: Samsung Electronics Co., Ltd.
Current Assignee Address: KR
Agency: Myers Bigel Sibley & Sajovec
Priority: KR2004-0043937 20040615
Main IPC: H01L21/3205
IPC: H01L21/3205 ; H01L21/4763

Methods of forming void-free layers in openings of semiconductor substrates

Abstract:

In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.

Abstract(Chinese):

在制造非易失性半导体存储器的浮置栅极的方法中，在衬底上形成图案以具有露出衬底的一部分的开口。在图案和基板的暴露部分上形成第一初步多晶硅层以基本上填充开口。通过部分地蚀刻第一初步多晶硅层直到形成在第一初步多晶硅层中的第一空穴露出来形成第一多晶硅层。在第一多晶硅层上形成第二多晶硅层。

Public/Granted literature

US20100048015A1 Methods of Forming Void-Free Layers in Openings of Semiconductor Substrates Public/Granted day:2010-02-25

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IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/18	...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料
H01L21/30	....用H01L21/20至H01L21/26各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/28）
H01L21/31	.....在半导体材料上形成绝缘层的，例如用于掩膜的或应用光刻技术的（密封层入H01L21/56）；以及这些层的后处理；这些层的材料的选择
H01L21/3205	......非绝缘层的沉积，例如绝缘层上的导电层或电阻层；这些层的后处理（电极的制造入H01L21/28）