Invention Grant
- Patent Title: Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection
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Application No.: US12378039Application Date: 2009-02-09
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Publication No.: US07902604B2Publication Date: 2011-03-08
- Inventor: Yi Su , Anup Bhalla , Daniel Ng
- Applicant: Yi Su , Anup Bhalla , Daniel Ng
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agent Bo-In Lin
- Main IPC: H01L23/62
- IPC: H01L23/62

Abstract:
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.
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Information query
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