Invention Grant
US07902679B2 Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
有权
芯片级封装的结构和制造方法，制造成本低，间距精细，焊锡凸块可靠性高
- Patent Title: Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
- Patent Title (中): 芯片级封装的结构和制造方法，制造成本低，间距精细，焊锡凸块可靠性高
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Application No.: US11981138Application Date: 2007-10-31
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Publication No.: US07902679B2Publication Date: 2011-03-08
- Inventor: Mou-Shiung Lin , Ming-Ta Lei , Chuen-Jye Lin
- Applicant: Mou-Shiung Lin , Ming-Ta Lei , Chuen-Jye Lin
- Applicant Address: TW Hsinchu
- Assignee: Megica Corporation
- Current Assignee: Megica Corporation
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.
Public/Granted literature
- US20080067677A1 Structure and manufacturing method of a chip scale package Public/Granted day:2008-03-20
Information query
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