In an embodiment, the present invention relates to an integrated circuit comprising at least one data signal input (data1, data2), at least one clock signal input (Clock), at least one control signal input (Cnt_del1, Cnt_del2) and a data signal output (Data_out). According to the invention, the integrated circuit is configured to provide a digital data signal having a variable symbol duration at its output (Data_out), the symbol duration being controllable by means of the control signal (Cnt_del1, Cnt_del2). A further embodiment of the invention relates to a method for generating a digital data signal having a variable symbol duration in which an output signal is generated by at least one first data signal, at least one first clock signal and at least one control signal. For this purpose, at least one second clock signal is generated from the first clock signal, the second clock signal having a variable delay and the delay being set depending on the value of the at least one control signal. The output signal is formed from the at least one first data signal, whereby the outputting is carried out edge-synchronously to the first and the second clock signal.