Invention Grant
- Patent Title: Booster circuit
- Patent Title (中): 增压电路
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Application No.: US12483702Application Date: 2009-06-12
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Publication No.: US07902911B2Publication Date: 2011-03-08
- Inventor: Atsushi Suzuki
- Applicant: Atsushi Suzuki
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2008-156913 20080616
- Main IPC: G05F1/10
- IPC: G05F1/10 ; G05F3/02

Abstract:
A booster circuit includes a first booster unit configured to boost a power supply voltage to a predetermined voltage value, a transfer gate transistor transferring the voltage received from the first booster unit to an output terminal, a switching transistor connected between an input terminal receiving the voltage from the first booster unit and a gate electrode of the transfer gate transistor, and a second booster unit configured to boost a voltage applied to a gate electrode of the switching transistor. The second booster unit includes an NMOS booster transistor. A drain electrode of the booster transistor is connected to the output terminal, a source terminal of the booster transistor is connected to a terminal to which a boosted voltage is to be applied, and a gate electrode of the booster transistor is connected to a booster capacitor.
Public/Granted literature
- US20090309651A1 BOOSTER CIRCUIT Public/Granted day:2009-12-17
Information query
IPC分类: