Invention Grant
- Patent Title: Non-volatile semiconductor memory device
- Patent Title (中): 非易失性半导体存储器件
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Application No.: US12398794Application Date: 2009-03-05
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Publication No.: US07903460B2Publication Date: 2011-03-08
- Inventor: Takeshi Kajimoto
- Applicant: Takeshi Kajimoto
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: McDermott Will & Emery LLP
- Priority: JP2008-095226 20080401
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states of each memory cell. In the logical erase state, a threshold voltage criterion of the memory cell is shifted to a state higher than the physical erase state. When data rewriting of the memory cell placed in the physical erase state is performed, a logical erase is performed and the threshold voltage criterion is shifted to a high voltage level. The logical erase simply shifts the voltage level of the threshold voltage criterion. Since an electrical charge accumulated in the memory cell is not moved, erasing can be done at high speed and in a short period of time.
Public/Granted literature
- US20090244976A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2009-10-01
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