Invention Grant
US07903497B2 Multi-port SRAM implemented with single-port 6-transistor memory cells coupled to an input multiplexer and an output demultiplexer
有权
使用耦合到输入多路复用器和输出解复用器的单端口6晶体管存储器单元实现的多端口SRAM
- Patent Title: Multi-port SRAM implemented with single-port 6-transistor memory cells coupled to an input multiplexer and an output demultiplexer
- Patent Title (中): 使用耦合到输入多路复用器和输出解复用器的单端口6晶体管存储器单元实现的多端口SRAM
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Application No.: US12258231Application Date: 2008-10-24
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Publication No.: US07903497B2Publication Date: 2011-03-08
- Inventor: Esin Terzioglu , Gil I. Winograd , Andreas Gotterba
- Applicant: Esin Terzioglu , Gil I. Winograd , Andreas Gotterba
- Applicant Address: US CA Aliso Viejo
- Assignee: Novelics, LLC
- Current Assignee: Novelics, LLC
- Current Assignee Address: US CA Aliso Viejo
- Agency: Haynes and Boone, LLP
- Main IPC: G11C8/16
- IPC: G11C8/16
Abstract:
In one embodiment, a multi-port SRAM is provided that comprises: a single input port and output port 6-T SRAM; and a multi-port control block circuit that includes: a plurality of input registers corresponding to a plurality of input ports to register corresponding input signals; an input multiplexer to select from the input registers to provide a selected input signal to the 6-T SRAM's single input port; a plurality of output registers corresponding to a plurality of output ports to register corresponding output signals; and an output de-multiplexer to select from the output registers to provide an output signal from the 6-T SRAM's single output port to the selected output register.
Public/Granted literature
- US20090190389A1 MULTI-PORT SRAM WITH SIX-TRANSISTOR MEMORY CELLS Public/Granted day:2009-07-30
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