Invention Grant
US07903668B2 STS frame-ATM cell circuit emulation apparatus and frame length compensation method for the same
失效
STS帧ATM信元电路仿真装置和帧长补偿方法相同
- Patent Title: STS frame-ATM cell circuit emulation apparatus and frame length compensation method for the same
- Patent Title (中): STS帧ATM信元电路仿真装置和帧长补偿方法相同
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Application No.: US12570595Application Date: 2009-09-30
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Publication No.: US07903668B2Publication Date: 2011-03-08
- Inventor: Souichi Kataoka , Ken Shiraishi
- Applicant: Souichi Kataoka , Ken Shiraishi
- Applicant Address: US CA Sunnyvale
- Assignee: Juniper Networks, Inc.
- Current Assignee: Juniper Networks, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Harrity & Harrity, LLP
- Priority: JP2000-159603 20000530
- Main IPC: H04L12/28
- IPC: H04L12/28

Abstract:
A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.
Public/Granted literature
- US20100020804A1 STS FRAME-ATM CELL CIRCUIT EMULATION APPARATUS AND FRAME LENGTH COMPENSATION METHOD FOR THE SAME Public/Granted day:2010-01-28
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