Invention Grant
US07904647B2 System for optimizing the performance and reliability of a storage controller cache offload circuit
有权
用于优化存储控制器高速缓存卸载电路的性能和可靠性的系统
- Patent Title: System for optimizing the performance and reliability of a storage controller cache offload circuit
- Patent Title (中): 用于优化存储控制器高速缓存卸载电路的性能和可靠性的系统
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Application No.: US11604631Application Date: 2006-11-27
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Publication No.: US07904647B2Publication Date: 2011-03-08
- Inventor: Mohamad H. El-Batal , Charles E. Nichols , John V. Sherman , Keith W. Holt , Jason M. Stuhlsatz
- Applicant: Mohamad H. El-Batal , Charles E. Nichols , John V. Sherman , Keith W. Holt , Jason M. Stuhlsatz
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Christopher P. Maiorana, PC
- Main IPC: G06F12/00
- IPC: G06F12/00
Abstract:
A method for offloading a cache memory is disclosed. The method generally includes the steps of (A) reading all of a plurality of cache lines from the cache memory in response to an assertion of a signal to offload of the cache memory, (B) generating a plurality of blocks by dividing the cache lines in accordance with a RAID configuration and (C) writing the blocks among a plurality of nonvolatile memories in the RAID configuration, wherein each of the nonvolatile memories has a write bandwidth less than a read bandwidth of the cache memory.
Public/Granted literature
- US20080126700A1 System for optimizing the performance and reliability of a storage controller cache offload circuit Public/Granted day:2008-05-29
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