Invention Grant
- Patent Title: Testing circuit split between tiers of through silicon stacking chips
- Patent Title (中): 测试电路分层穿过硅堆叠芯片
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Application No.: US12206977Application Date: 2008-09-09
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Publication No.: US07904770B2Publication Date: 2011-03-08
- Inventor: Thomas R. Toms
- Applicant: Thomas R. Toms
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Sam Talpalatsky; Nicholas J. Pauley; Jonathan T. Velasco
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/02 ; H01L23/58 ; H01L23/12 ; H01L23/34 ; H01L23/48
Abstract:
A method of testing a die having a non-testable circuit, where the non-testable circuit is logically incomplete and forms part of a logically complete multiple tier circuit. The method includes reconfiguring a tier-to-tier input point or tier-to-tier output point associated with a primary path of the non-testable circuit to create a logically complete secondary path for the tier-to-tier point such that the non-testable circuit can be tested. Testable dies and methods of preparing such dies are also provided.
Public/Granted literature
- US20100060312A1 Testing Circuit Split Between Tiers of Through Silicon Stacking Chips Public/Granted day:2010-03-11
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