Invention Grant
- Patent Title: Wafer scale testing using a 2 signal JTAG interface
- Patent Title (中): 使用2信号JTAG接口进行晶片刻度测试
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Application No.: US12849191Application Date: 2010-08-03
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Publication No.: US07904774B2Publication Date: 2011-03-08
- Inventor: Lee D. Whetsel
- Applicant: Lee D. Whetsel
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
Public/Granted literature
- US20100299569A1 WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE Public/Granted day:2010-11-25
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