Invention Grant
- Patent Title: Circuits with transient isolation operable in a low power state
- Patent Title (中): 具有瞬态隔离的电路可在低功耗状态下工作
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Application No.: US11839245Application Date: 2007-08-15
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Publication No.: US07904838B2Publication Date: 2011-03-08
- Inventor: Aris Balatsos , Charles Leung , Siva Raghu Ram Voleti
- Applicant: Aris Balatsos , Charles Leung , Siva Raghu Ram Voleti
- Applicant Address: CA Markham, Ontario
- Assignee: ATI Technologies ULC
- Current Assignee: ATI Technologies ULC
- Current Assignee Address: CA Markham, Ontario
- Agency: Vedder Price P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/45

Abstract:
An integrated circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch. The circuit also includes and a power consumption controller in communication with the core-logic, the latch and the isolation circuit, for controlling the latch to store a state of the core-logic output, and output a corresponding signal. The controller is further operable to signal the isolation circuit to isolate the core-logic output from the latch by providing an output corresponding to predetermined value and transition the core-logic from a high power state and a low power state. This prevents transient signals from propagating to interconnected circuit blocks and external devices.
Public/Granted literature
- US20090049321A1 CIRCUITS WITH TRANSIENT ISOLATION OPERABLE IN A LOW POWER STATE Public/Granted day:2009-02-19
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