Invention Grant
- Patent Title: Methods for partially removing circuit patterns from a multi-project wafer
- Patent Title (中): 从多工程晶圆部分去除电路图案的方法
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Application No.: US11536927Application Date: 2006-09-29
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Publication No.: US07904855B2Publication Date: 2011-03-08
- Inventor: Yi-Hong Tseng , Kuan-Liang Wu
- Applicant: Yi-Hong Tseng , Kuan-Liang Wu
- Applicant Address: JP Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: JP Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L21/00

Abstract:
Disclosed are a method and a system for partially removing circuit patterns from a multi-project wafer. This method and this system can be used to provide a multi-project-wafer to a user without disclosing proprietary circuit information of other customers. At least one integrated circuit design of a user is identified from a plurality of integrated circuit designs of a plurality of users. Those unidentified circuits can be totally removed through circuit removing method. Then the modified multi-project wafer can be delivered to the user without concerns about disclosing information of unidentified circuits which belongs to other customers. In one embodiment, a laser system may be used to totally remove the unidentified integrated circuit designs without impacting the circuit performance of identified circuits. In another embodiment, a diamond-blade saw may also be used to totally remove the unidentified integrated circuit designs without impacting the circuit performance of identified circuits.
Public/Granted literature
- US20070264798A1 Method and System for Partially Removing Circuit Patterns From a Multi-Project Wafer Public/Granted day:2007-11-15
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