An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. When creating a symbol library, if an FPGA subjected to create the symbol library is arranged in the circuit diagram, the library creating unit manages not to change a portion dividing and a pin layout of the existing symbol library arranged in the circuit diagram as much as possible. When arranging a symbol of the FPGA that a symbol library is newly created, a circuit-diagram reflecting unit arranges the symbol without changing the existing layout.