Invention Grant
- Patent Title: Integrating a boolean SAT solver into a router
- Patent Title (中): 将布尔SAT求解器集成到路由器中
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Application No.: US11732848Application Date: 2007-04-04
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Publication No.: US07904867B2Publication Date: 2011-03-08
- Inventor: Jerry R. Burch , Robert F. Damiano , Pei-Hsin Ho , James H. Kukula
- Applicant: Jerry R. Burch , Robert F. Damiano , Pei-Hsin Ho , James H. Kukula
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
One embodiment of the present invention provides a system that routes a set of pairs of points during the design of an integrated circuit (IC) chip. The system comprises a routing engine which is configured to search for a path to connect a current pair of points in the set of pairs of points, wherein the path comprises a set of rectangles and vertices. The routing engine uses a routing database, which keeps track of previously routed nets that can obstruct the routing of the current pair of points. The system further comprises a satisfiability (SAT) solver which is capable of solving a set of constraints, wherein the set of constraints are associated with the routability of the set of pairs of points. The SAT solver additionally comprises a SAT database which maintains the set of constraints and a current partial solution to the set of constraints. The SAT database is used to update the routing database if the current partial solution changes.
Public/Granted literature
- US20080250376A1 Integrating a boolean SAT solver into a router Public/Granted day:2008-10-09
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