Invention Grant
US07906363B2 Method of fabricating semiconductor device having three-dimensional stacked structure 有权
制造具有三维堆叠结构的半导体器件的方法

  • Patent Title: Method of fabricating semiconductor device having three-dimensional stacked structure
  • Patent Title (中): 制造具有三维堆叠结构的半导体器件的方法
  • Application No.: US11573976
    Application Date: 2005-08-19
  • Publication No.: US07906363B2
    Publication Date: 2011-03-15
  • Inventor: Mitsumasa Koyanagi
  • Applicant: Mitsumasa Koyanagi
  • Applicant Address: JP Tokyo
  • Assignee: ZyCube Co., Ltd.
  • Current Assignee: ZyCube Co., Ltd.
  • Current Assignee Address: JP Tokyo
  • Agency: Griffin & Szipl, P.C.
  • Priority: JP2004-240944 20040820
  • International Application: PCT/JP2005/015133 WO 20050819
  • International Announcement: WO2006/019156 WO 20060223
  • Main IPC: H01L21/00
  • IPC: H01L21/00
Method of fabricating semiconductor device having three-dimensional stacked structure
Abstract:
A method of fabricating a semiconductor device having a three-dimensional stacked structure by stacking semiconductor circuit layers on a support substrate, including the steps of: forming a trench in a semiconductor substrate; filling inside the trench with a conductive material to form a conductive plug; forming an element or circuit in an inside or on a surface of the semiconductor substrate where the conductive plug was formed; covering the surface of the semiconductor substrate where the element or circuit was formed with a second insulating film; and fixing the semiconductor substrate to the support substrate or a remaining one of the semiconductor circuit layers by joining the second insulating film to the support substrate or the remaining one of the semiconductor circuit layers through a wiring structure; selectively removing the semiconductor substrate to expose the first insulating film; and selectively removing the first insulating film.
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