Method for integrating silicon-on-nothing devices with standard CMOS devices

Invention Grant

US07906381B2 Method for integrating silicon-on-nothing devices with standard CMOS devices 有权

Title translation: 将无硅器件与标准CMOS器件集成的方法

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Patent Title: Method for integrating silicon-on-nothing devices with standard CMOS devices
Patent Title (中): 将无硅器件与标准CMOS器件集成的方法
Application No.: US12167282

Application Date: 2008-07-03
Publication No.: US07906381B2

Publication Date: 2011-03-15
Inventor: Nicolas Loubet , Didier Dutartre , Stéphane Monfray
Applicant: Nicolas Loubet , Didier Dutartre , Stéphane Monfray
Applicant Address: FR Montrouge FR Crolles
Assignee: STMicroelectronics S.A.,STMicroelectronics (Crolles 2) SAS
Current Assignee: STMicroelectronics S.A.,STMicroelectronics (Crolles 2) SAS
Current Assignee Address: FR Montrouge FR Crolles
Agency: Fleit Gibbons Gutman Bongini & Bianco P.L.
Agent Lisa K. Jorgenson; Stephen Bongini
Priority: FR0704870 20070705
Main IPC: H01L21/84
IPC: H01L21/84

Method for integrating silicon-on-nothing devices with standard CMOS devices

Abstract:

A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit.

Abstract(Chinese):

提供了一种用于在单个衬底中制造第一和第二类型的晶体管的方法。衬底的第一和第二活性区由横向隔离沟槽区限定，并且去除第二活性区的一部分，使得第二活性区位于第一活性区以下。第一和第二层半导体材料形成在第二有源区上，使得第二层基本上处于与第一活性区相同的平面。在第一活性区和第二层产生绝缘栅。选择性地去除至少一个隔离沟槽区域，并且选择性地去除第一层，以便在第二层下形成隧道。隧道填充有电介质材料以使第二层与衬底的第二活性区绝缘。还提供了这种集成电路。

Public/Granted literature

US20090032874A1 METHOD FOR INTEGRATING SILICON-ON-NOTHING DEVICES WITH STANDARD CMOS DEVICES Public/Granted day:2009-02-05

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/84	.....衬底不是半导体的，例如绝缘体