Invention Grant
US07906807B2 Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics
有权
在闪速存储器单元的位线结中使用聚合物间隔物和Si沟槽以改善TPD特性
- Patent Title: Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics
- Patent Title (中): 在闪速存储器单元的位线结中使用聚合物间隔物和Si沟槽以改善TPD特性
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Application No.: US12827069Application Date: 2010-06-30
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Publication No.: US07906807B2Publication Date: 2011-03-15
- Inventor: Ning Cheng , Calvin Gabriel , Angela Hui , Lei Xue , Harpreet Kaur Sachar , Phillip Lawrence Jones , Hiro Kinoshita , Kuo-Tung Chang , Huaqiang Wu
- Applicant: Ning Cheng , Calvin Gabriel , Angela Hui , Lei Xue , Harpreet Kaur Sachar , Phillip Lawrence Jones , Hiro Kinoshita , Kuo-Tung Chang , Huaqiang Wu
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Agency: Turocy & Watson, LLP
- Main IPC: H01L29/92
- IPC: H01L29/92 ; H01L29/76 ; H01L21/336

Abstract:
Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.
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