Invention Grant
US07906842B2 Wafer level system in package and fabrication method thereof 有权
封装中的晶圆级系统及其制造方法

  • Patent Title: Wafer level system in package and fabrication method thereof
  • Patent Title (中): 封装中的晶圆级系统及其制造方法
  • Application No.: US11828741
    Application Date: 2007-07-26
  • Publication No.: US07906842B2
    Publication Date: 2011-03-15
  • Inventor: Yun Mook Park
  • Applicant: Yun Mook Park
  • Applicant Address: KR Chungbuk
  • Assignee: NEPES Corporation
  • Current Assignee: NEPES Corporation
  • Current Assignee Address: KR Chungbuk
  • Agent Hosoon Lee
  • Priority: KR10-2007-0050661 20070525
  • Main IPC: H01L23/12
  • IPC: H01L23/12
Wafer level system in package and fabrication method thereof
Abstract:
There is provided a system-in-package (SiP), which includes a substrate obtained by cutting a wafer for each unit system; one or more first electronic devices mounted on the substrate by a heat radiation plate; a plurality of interlayer dielectrics sequentially formed on the substrate; and one or more second electronic devices buried between or in the interlayer dielectrics on the substrate. A heat sink may be additionally attached to the bottom surface of the substrate. In this case, a thermal conduction path including heat pipes connecting the heat radiation plate on the substrate and the heat sink is formed. In the SiP, various types of devices are buried at a wafer level, so that a more integrated semiconductor device is implemented corresponding to demand for a fine pitch. Further, the heat radiation of a device required in high-speed operation and high heat generation is maximized due to the multi-stepped heat radiation structure, and thus the operation of the device is more stabilized.
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