The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for providing a system clock to the master and slave. The clock generator determines whether the received data is correct on a cycle-by-cycle basis. The clock generator suppresses an edge of a next clock cycle of the system clock signal if the data is not to be correct. The clock generator allows the edge of a next clock cycle of the system clock signal if the data is correct.