Invention Grant
- Patent Title: Phase locked loop circuit that locks the oscillation frequency to a target frequency
- Patent Title (中): 将振荡频率锁定到目标频率的锁相环电路
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Application No.: US11813640Application Date: 2006-01-16
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Publication No.: US07907017B2Publication Date: 2011-03-15
- Inventor: Hideki Shirasu , Norio Kobayashi , Kouji Miyauchi
- Applicant: Hideki Shirasu , Norio Kobayashi , Kouji Miyauchi
- Applicant Address: JP Tokyo
- Assignee: Advantest Corporation
- Current Assignee: Advantest Corporation
- Current Assignee Address: JP Tokyo
- Agency: Greenblum & Bernstein P.L.C.
- Priority: JP2005-013138 20050120
- International Application: PCT/JP2006/300898 WO 20060116
- International Announcement: WO2006/077992 WO 20060727
- Main IPC: H03L7/001
- IPC: H03L7/001

Abstract:
In a PLL circuit, an oscillation frequency is quickly and accurately locked to a target frequency. There is provided a PLL circuit, including a VCO that controls the frequency of an output signal according to a voltage of an input signal, a loop divider that divides the frequency of a signal, which is acquired by causing a mixer to mix a local signal generated by a local oscillator and the output signal with each other, by N, and a reference frequency divider that divides the frequency of a reference signal, which is output by a reference signal oscillator, by R. Also provided is a phase comparator that outputs a signal according to a difference in phase between an output of the loop divider and an output of the reference frequency divider, a loop filter that passes low frequency components, and supplies the VCO with the low frequency components, a subtractor that outputs a difference between a voltage of the input signal to be supplied to the VCO so that the frequency coincides with a target value and the output of the loop filter, and switches that supply the loop filter with the output of the phase comparator or the output of the subtractor.
Public/Granted literature
- US20090004985A1 Signal Processing Apparatus Public/Granted day:2009-01-01
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