Invention Grant
- Patent Title: Phase noise minimized phase/frequency-locked voltage-controlled oscillator circuit
- Patent Title (中): 相位噪声最小相/锁频压控振荡电路
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Application No.: US12579149Application Date: 2009-10-14
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Publication No.: US07907018B2Publication Date: 2011-03-15
- Inventor: Stefano Pellerano , Ashoke Ravi , Yorgos Palaskas
- Applicant: Stefano Pellerano , Ashoke Ravi , Yorgos Palaskas
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Carrie A. Boone, P.C.
- Main IPC: H03L7/099
- IPC: H03L7/099

Abstract:
A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.
Public/Granted literature
- US20100033257A1 PHASE NOISE MINIMIZED PHASE/FREQUENCY-LOCKED VOLTAGE-CONTROLLED OSCILLATOR CIRCUIT Public/Granted day:2010-02-11
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