Invention Grant
- Patent Title: Pipelined A/D converter
- Patent Title (中): 流水线A / D转换器
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Application No.: US12463833Application Date: 2009-05-11
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Publication No.: US07907077B2Publication Date: 2011-03-15
- Inventor: Yasuo Morimoto
- Applicant: Yasuo Morimoto
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: McDermott Will & Emery LLP
- Priority: JP2008-182437 20080714
- Main IPC: H03M1/38
- IPC: H03M1/38

Abstract:
The present invention aims to provide a pipeline type A/D converter capable of realizing low power consumption while preventing a reduction in feedback factor of an amplifier. One embodiment of the present invention is of a pipeline type A/D converter which converts an analog signal to a digital signal, including a plurality of stages coupled in tandem and an error correction circuit which generates the digital signal, based on sub digital signals respectively outputted from the stages. When a sub digital signal of N bits is outputted at at least one of the stages in the pipeline type A/D converter according to the one embodiment of the present invention, the stage gain of a transfer function becomes 2N−K−1, the number of returns becomes 2N−2 and an integer K has a relation of 1≦K≦N.
Public/Granted literature
- US20100007542A1 PIPELINED TYPE A/D CONVERTER Public/Granted day:2010-01-14
Information query
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