Invention Grant
- Patent Title: Bare chip mounted structure and mounting method
- Patent Title (中): 裸芯片安装结构及安装方法
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Application No.: US11817991Application Date: 2006-03-07
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Publication No.: US07907420B2Publication Date: 2011-03-15
- Inventor: Koichi Nagai , Minoru Yamamoto , Ken Takano , Tatsuo Sasaoka , Kazumichi Shimizu
- Applicant: Koichi Nagai , Minoru Yamamoto , Ken Takano , Tatsuo Sasaoka , Kazumichi Shimizu
- Applicant Address: JP Osaka
- Assignee: PANASONIC Corporation
- Current Assignee: PANASONIC Corporation
- Current Assignee Address: JP Osaka
- Agency: Greenblum & Bernstein, P.L.C.
- Priority: JP2005-064780 20050309
- International Application: PCT/JP2006/304309 WO 20060307
- International Announcement: WO2006/095703 WO 20060914
- Main IPC: H05K1/11
- IPC: H05K1/11
Abstract:
A plurality of film substrates (2) having a bare chip (1) mounted on one side or both sides are joined into a laminated state by joint portions (3) and are attached to a motherboard (4) through junction by a joint portion (8) at a location off the mounting areas of the bare chips (1), thereby achieving a lower profile, higher lamination, and higher capacity.
Public/Granted literature
- US20080192423A1 Bare Chip Mounted Structure and Mounting Method Public/Granted day:2008-08-14
Information query
