Invention Grant
- Patent Title: Semiconductor memory device and method of testing same
- Patent Title (中): 半导体存储器件及其测试方法
-
Application No.: US12081013Application Date: 2008-04-09
-
Publication No.: US07907459B2Publication Date: 2011-03-15
- Inventor: Shunya Nagata
- Applicant: Shunya Nagata
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn Intellectual Property Law Group, PLLC
- Priority: JP2007-104828 20070412; JP2008-052165 20080303
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C8/00

Abstract:
Disclosed is a semiconductor memory device in which a cell is connected to word lines of at least first and second ports, and control of timing of activation of the word lines of the first and second ports is performed based upon first and second clock signals, respectively, comprising first and second test control signals in correspondence with the first and second clock signals that control the respective timings of activation of the word lines of the first and second ports. With regard to the cell with the first and second ports being selected, when the first test control signal is in an activated state and the second test control signal is in a deactivated state, control is exercised so as to mask the second clock signal and, responsive to the first clock signal, activate the first and second word lines simultaneously. When the second test control signal is in an activated state and the first test control signal is in a deactivated state, control is exercised so as to mask the first clock signal and, responsive to the second clock signal, activate the first and second word lines.
Public/Granted literature
- US20080253209A1 Semiconductor memory device and method of testing same Public/Granted day:2008-10-16
Information query