Provided is a test apparatus, including a storage section that stores a count value for adjusting a phase of a sampling clock indicating a timing of acquiring an output signal of a DUT; a clock generating section that generates the sampling clock indicating the timing of acquiring the output signal, based on an offset corresponding to the count value and on a reference clock; a first delay section that outputs a first delay clock having a frequency equal to the frequency of the sampling clock and a preset phase difference in relation to the sampling clock, based on the reference clock and the offset; a phase detecting section that detects a phase difference between the first delay clock and a transition point of the output signal, and changes the count value in a direction that decreases the phase difference; a timing comparison section that acquires the output signal according to a transition timing of the sampling clock; and a judging section that judges acceptability of the acquired output signal by comparing the output signal to an expected value.