A status holding circuit includes status holding sections of M stages (M is an integer equal to or more than 2) connected in series. Each of the status holding sections includes: N latches (N is an integer equal to or more than 2) provided for N input signals to N input terminals, respectively; and a switch circuit configured to set a data to a jth latch of the N latches in an ith status holding section of the M-stage status holding sections when a status signal is supplied to a jth input terminal of the N input terminals at an ith timing.