Invention Grant
- Patent Title: Hardware emulator having a selectable write-back processor unit
- Patent Title (中): 硬件仿真器具有可选择的回写处理器单元
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Application No.: US11601235Application Date: 2006-11-17
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Publication No.: US07908465B1Publication Date: 2011-03-15
- Inventor: Mitchell G. Poplack , Mikhail Bershteyn
- Applicant: Mitchell G. Poplack , Mikhail Bershteyn
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Moser IP Law Group
- Main IPC: G06F7/38
- IPC: G06F7/38 ; G06F9/00 ; G06F9/44 ; G06F15/00

Abstract:
A method and apparatus for emulating a hardware design comprising an instruction execution unit for executing at least one instruction, a memory for providing data to the instruction execution unit for processing into an output bit, and a write enable logic for controlling writing the output bit from the instruction execution unit to the memory. In this manner, the output bit produced by the instruction execution unit executing an instruction may be selectably stored in memory to facilitate efficient processing of conditional emulation operations.
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