Invention Grant
- Patent Title: Processor to JTAG test access port interface
- Patent Title (中): 处理器到JTAG测试访问端口接口
-
Application No.: US12203109Application Date: 2008-09-02
-
Publication No.: US07908533B2Publication Date: 2011-03-15
- Inventor: Senthil Somasundaram , Jun Qian
- Applicant: Senthil Somasundaram , Jun Qian
- Applicant Address: US CA San Jose
- Assignee: Cisco Technology, Inc.
- Current Assignee: Cisco Technology, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
Method and apparatus for operating for operating an Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1 compliant Joint Test Action Group (JTAG) Test Access Port (TAP) controller are disclosed. An example apparatus includes write logic that is configured to operationally interface with a TAP controller and a processor. The write logic is further configured to receive, from the processor, data for initializing the apparatus and operating the TAP controller, convert at least a portion of the data from a parallel format to a serial format and communicate the converted data to the TAP controller.
Public/Granted literature
- US20100058130A1 PROCESSOR TO JTAG TEST ACCESS PORT INTERFACE Public/Granted day:2010-03-04
Information query