Invention Grant
US07908533B2 Processor to JTAG test access port interface 有权
处理器到JTAG测试访问端口接口

Processor to JTAG test access port interface
Abstract:
Method and apparatus for operating for operating an Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1 compliant Joint Test Action Group (JTAG) Test Access Port (TAP) controller are disclosed. An example apparatus includes write logic that is configured to operationally interface with a TAP controller and a processor. The write logic is further configured to receive, from the processor, data for initializing the apparatus and operating the TAP controller, convert at least a portion of the data from a parallel format to a serial format and communicate the converted data to the TAP controller.
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