Invention Grant
- Patent Title: Method of anti-stiction dimple formation under MEMS
- Patent Title (中): MEMS下抗静电凹坑形成方法
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Application No.: US11932099Application Date: 2007-10-31
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Publication No.: US07919006B2Publication Date: 2011-04-05
- Inventor: Woo Tae Park , Hemant D. Desai
- Applicant: Woo Tae Park , Hemant D. Desai
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Daniel D. Hill; Michael J. Balconi-Lamica
- Main IPC: C03C15/00
- IPC: C03C15/00 ; H01L21/302

Abstract:
A method for making a MEMS structure comprises patterning recesses in a dielectric layer overlying a substrate, each recess being disposed between adjacent mesas of dielectric material. A conformal layer of semiconductor material is formed overlying the recesses and mesas. The conformal layer is chemical mechanically polished to form a chemical mechanical polished surface, wherein the chemical mechanical polishing is sufficient to create dished portions of semiconductor material within the plurality of recesses. Each dished portion has a depth proximate a central portion thereof that is less than a thickness of the semiconductor material proximate an outer portion thereof. A semiconductor wafer is then bonded to the chemical mechanical polished surface. The bonded semiconductor wafer is patterned with openings according to the requirements of a desired MEMS transducer. Lastly, the MEMS transducer is released. Releasing advantageously exposes anti-stiction features formed from outer edges of the dished portion of semiconductor material.
Public/Granted literature
- US20090111267A1 METHOD OF ANTI-STICTION DIMPLE FORMATION UNDER MEMS Public/Granted day:2009-04-30
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