Invention Grant
US07919347B2 Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes
有权
制造P-I-N二极管的方法,P-I-N二极管的结构和P-I-N二极管的设计结构
- Patent Title: Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes
- Patent Title (中): 制造P-I-N二极管的方法,P-I-N二极管的结构和P-I-N二极管的设计结构
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Application No.: US12349018Application Date: 2009-01-06
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Publication No.: US07919347B2Publication Date: 2011-04-05
- Inventor: Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens , William Robert Tonti
- Applicant: Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens , William Robert Tonti
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Schmeiser, Olsen & Watts
- Agent Anthony J. Canale
- Main IPC: H01L29/868
- IPC: H01L29/868

Abstract:
Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.
Public/Granted literature
- US20100173449A1 METHODS OF FABRICATING P-I-N DIODES, STRUCTURES FOR P-I-N DIODES AND DESIGN STRUCTURE FOR P-I-N DIODES Public/Granted day:2010-07-08
Information query
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