Invention Grant
US07919384B2 Method of making planar-type bottom electrode for semiconductor device
有权
制造半导体器件的平面型底电极的方法
- Patent Title: Method of making planar-type bottom electrode for semiconductor device
- Patent Title (中): 制造半导体器件的平面型底电极的方法
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Application No.: US12050649Application Date: 2008-03-18
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Publication No.: US07919384B2Publication Date: 2011-04-05
- Inventor: Hsiao-Che Wu , Ming-Yen Li , Wen-Li Tsai
- Applicant: Hsiao-Che Wu , Ming-Yen Li , Wen-Li Tsai
- Applicant Address: TW Hsinchu
- Assignee: ProMOS Technologies Inc.
- Current Assignee: ProMOS Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Muncy, Geissler, Olds & Lowe, PLLC
- Priority: TW96126042A 20070717
- Main IPC: H01L21/20
- IPC: H01L21/20

Abstract:
A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.
Public/Granted literature
- US20090023264A1 METHOD OF MAKING PLANAR-TYPE BOTTOM ELECTRODE FOR SEMICONDUCTOR DEVICE Public/Granted day:2009-01-22
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