The present invention provides a memory device including at least two of a first dielectric on a semiconductor substrate; a floating gates corresponding to each of the at least two gate oxides; a second dielectric on the floating gates; a control gate conductor formed atop the second gate oxide; source and drain regions present in portions of the semiconducting substrate that are adjacent to each portion of the semiconducting substrate that is underlying the at least two of the first gate oxide, wherein the source and drain regions define a length of a channel positioned therebetween; and a low-k dielectric material that is at least present between adjacent floating gates of the floating gates corresponding to each of the at least two gate oxides, wherein the low-k dielectric material is present along a direction perpendicular to the length of the channel positioned therebetween.