Invention Grant
US07919388B2 Methods for fabricating semiconductor devices having reduced gate-drain capacitance
有权
制造具有降低的栅 - 漏电容的半导体器件的方法
- Patent Title: Methods for fabricating semiconductor devices having reduced gate-drain capacitance
- Patent Title (中): 制造具有降低的栅 - 漏电容的半导体器件的方法
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Application No.: US12627739Application Date: 2009-11-30
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Publication No.: US07919388B2Publication Date: 2011-04-05
- Inventor: Ljubo Radic , Edouard D. de Frésart
- Applicant: Ljubo Radic , Edouard D. de Frésart
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L29/72
- IPC: H01L29/72

Abstract:
Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging regions of the etch mask extending partially over the trench, and depositing a gate electrode material into the trench and onto the overhanging regions. The gate electrode material merges between the overhanging regions prior to the filling of the trench to create an empty fissure within the trench. A portion of the semiconductor substrate is removed through the empty fissure to form a void cavity proximate the trench.
Public/Granted literature
- US20100084705A1 SEMICONDUCTOR DEVICES HAVING REDUCED GATE-DRAIN CAPACITANCE AND METHODS FOR THE FABRICATION THEREOF Public/Granted day:2010-04-08
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