Invention Grant
- Patent Title: Semiconductor device and method of manufacturing the same
- Patent Title (中): 半导体装置及其制造方法
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Application No.: US12403881Application Date: 2009-03-13
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Publication No.: US07919824B2Publication Date: 2011-04-05
- Inventor: Syotaro Ono , Wataru Saito , Nana Hatano , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Miho Watanabe
- Applicant: Syotaro Ono , Wataru Saito , Nana Hatano , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Miho Watanabe
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2008-076588 20080324
- Main IPC: H01L27/088
- IPC: H01L27/088

Abstract:
A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.
Public/Granted literature
- US20090236697A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2009-09-24
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