Invention Grant
US07919858B2 Semiconductor device having lands disposed inward and outward of an area of a wiring board where electrodes are disposed
有权
具有设置在配置有电极的布线基板的区域的内侧和外侧的平台的半导体装置
- Patent Title: Semiconductor device having lands disposed inward and outward of an area of a wiring board where electrodes are disposed
- Patent Title (中): 具有设置在配置有电极的布线基板的区域的内侧和外侧的平台的半导体装置
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Application No.: US12432057Application Date: 2009-04-29
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Publication No.: US07919858B2Publication Date: 2011-04-05
- Inventor: Tadatoshi Danno
- Applicant: Tadatoshi Danno
- Applicant Address: JP Kawasaki
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki
- Agency: Mattingly & Malur, P.C.
- Priority: JP2008-153988 20080612
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/04 ; H01L23/053 ; H01L23/12
Abstract:
The present invention provides a technique capable of suppressing variations in the height of each solder ball where an NSMD is used as a structure for each land. Vias that extend through a wiring board are provided. Lands are formed at the back surface of the wiring board so as to be coupled directly to the vias respectively. The lands are respectively formed so as to be internally included in openings defined in a solder resist. Half balls are mounted over the lands respectively. Namely, the present invention has a feature in that the configuration of coupling between each of the lands and its corresponding via both formed at the back surface of the wiring board is taken as a land on via structure and a configuration form of each land is taken as an NSMD.
Public/Granted literature
- US20090309210A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2009-12-17
Information query
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