Invention Grant
US07919860B2 Semiconductor device having wafer level chip scale packaging substrate decoupling
有权
具有晶圆级芯片级封装衬底去耦的半导体器件
- Patent Title: Semiconductor device having wafer level chip scale packaging substrate decoupling
- Patent Title (中): 具有晶圆级芯片级封装衬底去耦的半导体器件
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Application No.: US12048294Application Date: 2008-03-14
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Publication No.: US07919860B2Publication Date: 2011-04-05
- Inventor: Rajen M. Murugan , Robert F. McCarthy , Baher S. Haroun , Peter R. Harper
- Applicant: Rajen M. Murugan , Robert F. McCarthy , Baher S. Haroun , Peter R. Harper
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Yingsheng Tung; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.
Public/Granted literature
- US20090057889A1 Semiconductor Device Having Wafer Level Chip Scale Packaging Substrate Decoupling Public/Granted day:2009-03-05
Information query
IPC分类:
