Invention Grant
- Patent Title: Reducing resistivity in interconnect structures of integrated circuits
- Patent Title (中): 降低集成电路互连结构中的电阻率
-
Application No.: US11429879Application Date: 2006-05-08
-
Publication No.: US07919862B2Publication Date: 2011-04-05
- Inventor: Cheng-Lin Huang
- Applicant: Cheng-Lin Huang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/52
- IPC: H01L23/52
Abstract:
An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.
Public/Granted literature
- US20070257369A1 Reducing resistivity in interconnect structures of integrated circuits Public/Granted day:2007-11-08
Information query
IPC分类:
