Invention Grant
- Patent Title: Forming of the last metallization level of an integrated circuit
- Patent Title (中): 形成集成电路的最后一个金属化水平
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Application No.: US10791136Application Date: 2004-03-02
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Publication No.: US07919864B2Publication Date: 2011-04-05
- Inventor: Jacky Seiller , Jean-François Revel , Claude Douce
- Applicant: Jacky Seiller , Jean-François Revel , Claude Douce
- Applicant Address: FR Montrouge
- Assignee: STMicroelectronics S.A.
- Current Assignee: STMicroelectronics S.A.
- Current Assignee Address: FR Montrouge
- Agency: Wolf, Greenfield & Sacks, P.C.
- Agent Lisa K. Jorgenson; James H. Morris
- Priority: FR0350672 20031013
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L21/4763

Abstract:
An integrated circuit including one or several metallization levels, metal conductive strips and metal contact pads being formed on the last metallization level, the last level being covered with a passivation layer in which are formed openings above the contact pads. The thickness of the pads, at least at the level of their portions not covered by the passivation layer, is smaller than the thickness of said conductive strips.
Public/Granted literature
- US20050077626A1 Forming of the last metallization level of an integrated circuit Public/Granted day:2005-04-14
Information query
IPC分类: