Invention Grant
- Patent Title: Post passivation interconnection schemes on top of IC chip
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Application No.: US11854561Application Date: 2007-09-13
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Publication No.: US07919865B2Publication Date: 2011-04-05
- Inventor: Mou-Shiung Lin , Jin-Yuan Lee
- Applicant: Mou-Shiung Lin , Jin-Yuan Lee
- Applicant Address: TW Hsinchu
- Assignee: Megica Corporation
- Current Assignee: Megica Corporation
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L23/528
- IPC: H01L23/528

Abstract:
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
Public/Granted literature
- US20080061444A1 Post passivation interconnection schemes on top of IC chip Public/Granted day:2008-03-13
Information query
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