Invention Grant
- Patent Title: Integrated circuit design based on scan design technology
- Patent Title (中): 基于扫描设计技术的集成电路设计
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Application No.: US12219742Application Date: 2008-07-28
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Publication No.: US07919981B2Publication Date: 2011-04-05
- Inventor: Kazuyuki Irie
- Applicant: Kazuyuki Irie
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: RENESAS Electronics Corporation
- Current Assignee: RENESAS Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2007-198617 20070731
- Main IPC: H03K19/173
- IPC: H03K19/173

Abstract:
An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within the scan chain, and a scan output terminal connected to another scan data line within the scan chain. The dummy block is configured to output data on the scan output terminal in response to input data fed to the scan input terminal, not responsively to the clock signal.
Public/Granted literature
- US20090032899A1 Integrated circuit design based on scan design technology Public/Granted day:2009-02-05
Information query
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