Invention Grant
- Patent Title: Digital phase locked loop with dithering
- Patent Title (中): 数字锁相环与抖动
-
Application No.: US12841354Application Date: 2010-07-22
-
Publication No.: US07920081B2Publication Date: 2011-04-05
- Inventor: Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
- Applicant: Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03M1/06
- IPC: H03M1/06

Abstract:
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
Public/Granted literature
- US20100283654A1 DIGITAL PHASE LOCKED LOOP WITH DITHERING Public/Granted day:2010-11-11
Information query