Invention Grant
- Patent Title: ESD configuration for low parasitic capacitance I/O
- Patent Title (中): ESD配置用于低寄生电容I / O
-
Application No.: US12393417Application Date: 2009-02-26
-
Publication No.: US07920366B2Publication Date: 2011-04-05
- Inventor: Chun-Ying Chen , Agnes Neves Woo
- Applicant: Chun-Ying Chen , Agnes Neves Woo
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H02H9/00
- IPC: H02H9/00

Abstract:
An integrated circuit can include an I/O pad, an internal circuit, an inductor, an electrostatic discharge (ESD) protection circuit, and an ESD clamp. The internal circuit can be biased with a first voltage supply and a second voltage supply, where the internal circuit is connected to the I/O pad at a first node. The ESD protection circuit can be connected between the first node and a second node. The inductor can be connected between the second node and a third voltage supply. Further, the ESD clamp can be connected between the second node and the second voltage supply.
Public/Granted literature
- US20090161276A1 ESD Configuration for Low Parasitic Capacitance I/O Public/Granted day:2009-06-25
Information query