Invention Grant
US07920366B2 ESD configuration for low parasitic capacitance I/O 有权
ESD配置用于低寄生电容I / O

ESD configuration for low parasitic capacitance I/O
Abstract:
An integrated circuit can include an I/O pad, an internal circuit, an inductor, an electrostatic discharge (ESD) protection circuit, and an ESD clamp. The internal circuit can be biased with a first voltage supply and a second voltage supply, where the internal circuit is connected to the I/O pad at a first node. The ESD protection circuit can be connected between the first node and a second node. The inductor can be connected between the second node and a third voltage supply. Further, the ESD clamp can be connected between the second node and the second voltage supply.
Public/Granted literature
Information query
Patent Agency Ranking
0/0