Circuitry for performing a set or reset process for a reversible resistance-switching memory element in a memory device. A ramped voltage is applied to the memory cell and its state is constantly monitored so that the voltage can be discharged as soon as the set or reset process is completed, avoiding possible disturbs to the memory cell. One set circuit ramps the voltage using a current source, while detecting a current peak using an op-amp loop. One reset circuit ramps the voltage using an op-amp loop, while detecting a current peak by continuing to draw current at the peak current to maintain the output signal stable. Another set circuit ramps the voltage using an op-amp loop and a source-follower configuration. Another reset circuit ramps the voltage using an op-amp loop and a source-follower configuration with level shifting to reduce power consumption. Faster detection and shutoff, and stable operation, are achieved.